Specification (Spec)

Features
Performance
Latencies
Bandwidths
Power
Clock Frequencies

Testability

Scan
JTAG
BIST
IDDQ

Fab Process
IO Interfaces
Package
Schedule
Levels of Abstraction

Gate
Basic transistor to Boolean logic abstraction
Simple gates, sequential cells, IO cells

RTL

Procedural Language
Parallelism
Clock-driven

Behavioral

Function without clocks

Static Timing

Fast Best/Worst Path analysis
Clock frequency plus top-level IO constraints
Combinational Path Calculation
Setup/Hold calculation
False Paths
Histogram Example
Performance

Libraries

Functional
Timing/Power
Physical
Memories
Library Development

Typical Cell List
Physical Design
Area
Power
Timing

Characterization

Delay and Power Abstraction d = f(pvtsl)
Accuracy goals
PWL, Tables, Polynomials
Characterization Boundaries
Input and Output Capacitance
Timing arcs
Pin State Dependencies
Setup, Hold, Min Pulse

View/Tool Support

Logical
Timing with backannotation support
Power
Physical  

Architectural Building Blocks

Combinational Logic
State Machines
Counters
Binary
LSF
Grey
Fifos
Synchronous
Asynchronous
On-Chip Memories
Single/Multi Port
Clock Domain Crossing
Arbiters

Block Development

Partitioning
Clock Domain Isolation
Prototyping Issues
Timing Constraint Issues
Tool Capacity Issues

SOC Development

IP Views
Block Interfacing
Loading
Timing
Drive
Clock Planning
Reset Strategy
Top-Level Timing       
PLLs

Performance Modeling

Performance Constraints
Information Bandwidth
Interface Modeling
Computation Rate Modeling
Queues
Performance Metrics

Design for Test

Scan
BIST
JTAG
Yields

Design for Power

Power Estimation
Package Power Calculations
Sources of Power
Transistor/Gate Sizing
Low Power Clocking Techniques
Low Voltage IO Technique

Design Capture

Text Tools
Graphical Tools
Coding Guidelines

Synthesis

Mapping function to gates
Optimizations
Area
Mapping search
Boolean reductions
Resource sharing
Timing
Mapping search
Restructuring inputs
Resource Sharing
Wire Estimation
Wireload models
Manhattan route estimate
Constraints
Synthesis Processes
Constraint Analysis

Design Checking

Syntax Checking
Rule Checking
Synthesis Rules
Testability Rules
Linking
Constraint Completeness

Physical Design

Floor planning

Hard Block
Group/Region
Hierarchical

Power Planning

Electromigration
VDD/VSS Rule

Place and Route

Placement Algorithms
Timing Driven Features
Global/Detail Route

Antenna Fixing
Extraction

2D, 2D+, or 3D Solver
RC tree reduction

Delay Calculation
Backannotation/Static Analysis
LVS
DRC
Timing Closure

Front-End-Back-End Handoffs
Reoptimization
Manual Override Techniques

Verification Processes

Simulator Technologies

Event Driven
Cycle-based

Verification Techniques
Stimulus Development
Random
Directed
Response Checking

Assertion Checking

OVL Assertion Library

Result Prediction Techniques

Parallel Model
Golden Response Comparison

Result Monitoring

Watchers
Code Coverage
Test Plan Matrix
Debugging Methods
Waveform Tools

Regression Environments

Model Bring Up Strategy

Interface Development
Behavior Development

Test Plan Development
Test Bench Development

Block Level
System Level

Bringing Up System Level Simulations

Formal Verification

Equivalence Checking
Rule Checking

Validation With Prototypes

Hardware Accelerators
Emulators
FPGA Systems
Stimulus Generation
Debug Issues